In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (μP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. An SOC device integrates into a single chip many of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the system.
System-on-a-chip (SOC) data processors are characterized by a very high degree of integration on a single integrated circuit (IC) chip. Many of the peripheral components now integrated onto the same IC chip as a processor core would have been implemented as separate IC chips in a previous generation of processors. Advantageously, this decreases the amount of board space required, reduces the effects of noise, allows for low-voltage operations, and, in many cases, reduces the pin count of the SOC device.
System-on-a-chip (SOC) devices comprise a plurality of individual modules that communicate with each other by sending data over one or more internal data buses. Many of the individual modules in a system-on-a-chip device function independently of each other. The independent functioning of the modules often causes the modules to simultaneously attempt to access memory through a memory controller of the system-on-a-chip device. The data bus that connects the modules to the memory controller is provided with a memory access arbiter unit to decide which memory request will be granted priority to the memory controller.
The arbitration scheme of a memory access arbiter unit may be either fixed or adaptive. In a fixed arbitration scheme the memory access priorities are not changed after they are assigned to each module. For example, in most types of fixed arbitration schemes the highest memory access priority is assigned to the central processing unit (CPU) module. Lower memory access priorities are then assigned to other modules of the computer system. Whenever the memory controller simultaneously receives two or more memory access requests the memory controller simply grants access to the module with the highest memory access priority. The memory access priorities remain fixed for each module.
In an adaptive arbitration scheme the memory access priorities may be changed after they are assigned to each module. An example of an adaptive arbitration scheme is set forth in U.S. Pat. No. 6,286,083. In an adaptive arbitration scheme, memory access requests that are refused service are adaptively assigned progressively higher priority rankings until they are granted service. As in the case of a fixed arbitration scheme, whenever the memory controller simultaneously receives two or more memory access requests the memory controller simply grants access to the module with the highest memory access priority. But in an adaptive arbitration scheme, the memory access priorities do not remain fixed for each module.
A system-on-a-chip device comprises a plurality of individual data streams to and from the individual modules of the device. There is therefore a need to provide an acceptable level of memory access latency. One contributor to variable memory access latency is caused by the execution of memory refresh requests. When a typical prior art memory controller receives a memory refresh request, the memory controller immediately executes the memory refresh request. The memory controller suspends the execution of all other memory transactions while the memory refresh request is being processed. The suspension of all other memory transactions causes unexpected delays and causes increased memory access latency.
Therefore, there is a need in the art for an apparatus and method that is capable of scheduling the execution of memory refresh requests to minimize memory access latency. In particular, there is a need in the art for improved system-on-a-chip (SOC) devices and other large-scale integrated circuits that have a memory controller that is capable of scheduling the execution of memory refresh requests to minimize memory access latency.